Electronic devices comprising bottom-gate TFTs and their manufacture

ABSTRACT

A method of manufacturing an electronic device comprising a bottom-gate TFT ( 12 ) is provided, the method comprising the steps of: forming a doped amorphous silicon gate layer ( 26 ′) on a substrate, the gate layer defining a gate ( 26 ), forming a gate insulating layer ( 32 ) over the gate, forming an amorphous silicon active layer ( 28 ′) over the gate insulating layer and overlying at least part of the gate, and annealing the amorphous silicon active layer to form a polysilicon active layer ( 28 ). A thinner gate insulating layer can be used giving a TFT having a low threshold voltage.

This invention relates to electronic devices comprising thin-filmtransistors (hereinafter termed “TFTs”) and, in particular,polycrystalline silicon (hereinafter termed polysilicon) bottom-gateTFTs each having a gate, a gate insulating layer and a polysiliconactive layer overlying the gate. The device may be, for example, anactive matrix display device, a sensing array or a thin-film datastorage device. The invention also relates to methods of manufacturingsuch an electronic device comprising a bottom-gate TFT.

There is increasing interest in developing polysilicon TFTs for largearea electronics applications such as the addressing circuitry in activematrix flat panel displays as described in U.S. Pat. No. 5,130,829 towhich reference is invited. In general, polysilicon TFTs offer a fasteraddressing speed than TFTs fabricated with amorphous silicon activelayers. Polysilicon active layers are conventionally formed by anannealing process in which an amorphous silicon layer is melted, bylaser for example, and allowed to cool reforming into a poly-crystallinestructure. In the case of an array of TFTs, the active layer may bepatterned into individual active islands for each TFT either before orafter the annealing process. A more detailed description ofpolycrystallisation of silicon by laser annealing is given in the paperby S. D. Brotherton et al, “Influence of melt depth in lasercrystallized poly-Si thin film transistors”, J. Appl. Phys, 82 (8),pages 4086 to 4094, (1997), to which reference is invited.

For the purposes of this description, the term “amorphous” relates tomaterials in which the constituent atoms are randomly positioned. Theterm “polycrystalline” relates to materials which comprise a pluralityof monocrystals, a monocrystal having a regular repeating latticestructure of its constituent atoms. This is particularly relevant topolycrystalline silicon, or polysilicon, which is commonly formed bymelting and cooling amorphous silicon. Typical grain sizes forpolysilicon lie between 0.1 μm and 5 μm. However, when crystallisedunder certain conditions, the silicon can have a grain size on amicroscopic scale, typically 0–0.5 μm. The term “microcrystalline”relates to crystalline materials having grain sizes on a microscopicscale.

There is particular interest in fabricating TFTs having low thresholdvoltages. Circuits comprising such devices can operate at lower voltagesand, due to their small size, can operate at a greater speed. Lowthreshold voltages can be achieved by reducing the thickness of the gateinsulating layers, or dielectrics, formed between the gate of a TFT andthe polysilicon active layer. However, as the gate insulating layersbecome thinner, the greater the requirement for a smooth interfacebetween the surfaces of the gate insulating layer and its adjacentlayers.

The annealing process required to polycrystallise the amorphous siliconlayers severely roughens the top surface thereof. This is described inmore detail in the paper by McCulloch et al, Appl Phys Lett, 66, 16,pages 2060 to 2062, (1995), to which reference is invited.

In top-gated TFT devices, in which the gate overlies the active layer,the roughened top surface of the active layer is adjacent the gateinsulating layer. This limits the use of thin gate insulating layersbecause deformities at the interface cause weak spots at whichelectrical breakdown may occur.

It may be thought that bottom-gated TFT devices, in which the activelayer overlies the gate and the roughened (top) surface of the activelayer is remote from the gate insulating layer would be more suited thantop-gated devices to using a thinner gate insulating layer. However, theroughness of the surface of the underlying gate can also be a limitingfactor. Gates formed from metal, such as aluminium for example, areknown to deform or melt when subjected to the heat conducted via theupper layers during the annealing process. During this process, theactive layer, formed initially as amorphous silicon, is subjected to anenergy beam which melts the silicon through the whole thickness of thelayer. The integrity of the gate material must survive this annealingprocess. However, due to the low melting point of some conventionallyused metals, the gate can be caused to melt or evaporate. This can leadto hillock formation causing “spiking” in which the top surface of themetal gate becomes roughened to the extent that it penetrates throughthe gate insulating layer causing electrical breakdown of the TFT. Also,the difference in mechanical properties between the layers in the devicestack can cause the gate to delaminate through heating, mechanicalstress or adhesion failure.

U.S. Pat. No. 6,025,218, the contents of which is included herein asreference material, describes a method of manufacturing a TFT devicehaving a laminated bottom-gate electrode comprising a metal film and aless conductive film. In an embodiment described in U.S. Pat. No.6,025,218 the gate comprises a laminated conductor having a metal filmand a semiconductor film which may comprise amorphous silicon. Aninsulating film covers at least part of the laminated conductor andextends below a semiconductor island. The semiconductor film is said toprovide protection for the metal film of the laminated conductor from anenergy beam during the crystallisation of the semiconductor material ofthe island. However, on a microscopic scale, thin film metals have roughsurfaces which result from the formation of many separate crystallitesduring the deposition, giving the metal film a polycrystalline nature.The vertical scale of the roughness of metal films can be 10–25% of thefilm thickness. Additionally, thin metal films can be pin-holed. Moreimportantly, the changes in surface from one grain to another can bequite angular (large values of curvature=d²y/dx², where y is thevertical parameter and x is the lateral parameter in a 2-D model). Thiscan cause coverage problems giving rise to local high field points whichmay result in electrical breakdown across a thin overlying gateinsulating layer even if protected by a semiconductor layer as in U.S.Pat. No. 6,025,218.

It is an object of the present invention to provide an improved methodof manufacturing an electronic device comprising a bottom gatepolysilicon TFT which at least partially alleviates the aforementionedproblems associated with using thinner gate insulating layers.

According to one aspect of the present invention there is provided amethod of manufacturing an electronic device comprising a bottom-gateTFT, the method comprising the steps of:

-   -   forming a doped amorphous silicon gate layer on a substrate, the        gate layer defining a gate;    -   forming a gate insulating layer over the gate;    -   forming an amorphous silicon active layer over the gate        insulating layer and overlying at least part of the gate; and,    -   annealing the amorphous silicon active layer to form a        polysilicon active layer.

This results in an improved bottom-gate TFT having a low thresholdvoltage. By using doped amorphous silicon for the gate layer, smoothfilm can be deposited directly onto the substrate allowing a smoothinterface with the overlying gate insulating layer, as desirable forTFTs having low threshold voltages. Doped amorphous silicon has a highermelting point than most metals used conventionally for gates. Therefore,the risk of hillock formation leading to spiking is reduced as the gatematerial is less likely to deform during the annealing process even ifthis layer gets heated. The mechanical properties of the gate materialare similar to those of the other layers in the device stack.Advantageously this reduces the risk of delamination of the gate whenheated.

The annealing of the amorphous silicon active layer may cause at leastan upper surface region of the gate layer to become microcrystallinethrough solid phase crystallisation as a result of heating of the gatelayer material during the annealing process. The surface of themicrocrystalline layer remains smooth. Advantageously, this can increasethe conductivity of the gate layer material.

The doped amorphous silicon gate layer need not be completely covered bythe amorphous silicon active layer, and a portion may be left exposed tothe energy beam. The exposed portion of the gate layer may then becomepolycrystalline through the annealing process. Advantageously, this maybe used to reduce the resistance of, for example, connections to thegate which can reduce the charging time of the gate.

Preferably, the edges of the gate are tapered such that they slopeoutwardly towards the substrate. This avoids step coverage problems andensures good coverage of the gate by the gate insulating layer, and isparticularly important when using a relatively thin gate insulatinglayer. Preferably, the angle made between at least one of the taperededges of the gate and the substrate is between 10° and 30°. Dry etchingmay, for example, be used to form the tapered edges.

The gate insulating layer may comprise silicon oxide, silicon nitride,tantalum oxide, aluminium oxide, titanium oxide, hafnium oxide,zirconium oxide, an alloy of any of these materials, or any othersuitable material with a high dielectric constant.

In a preferred embodiment, the thickness of the doped amorphous silicongate layer is between 5 nm and 10 nm, the thickness of the gateinsulating layer is between 1 nm and 40 nm, and the thickness of theamorphous silicon active layer is between 10 nm and 100 nm.Advantageously, the gate insulating layer is made as thin as ispracticably possible for an operational TFT and has a thickness in therange of 1 nm to 5 nm. This gives TFTs with low threshold values whichis particularly beneficial when used in arrays for low-power activematrix devices. Also, the size of the TFTs can be scaled down to allowhigher resolution active matrix devices to be fabricated.

The method may further comprise the step of forming a top-gate overlyingat least part of the polysilicon active layer, (the top-gate for examplecontacting with the bottom-gate via a contact hole). This produces adual-gate TFT which offers an even lower threshold voltage than thecorresponding single-gate TFT, together with a higher on-current andlower off-current.

The electronic device may comprise an active plate for an active matrixdevice, such as a liquid crystal display, electroluminescent display,sensor array or data storage device. The active plate may comprise anarray of TFTs arranged in rows and columns. For such purposes, themethod may further comprise the step of forming a set of row conductors,each row conductor contacting with a plurality of gates in the same row.These may be formed before the gate layer so that they lie between thegate layer and the substrate. Alternatively, the row conductors may beformed over the TFT and contact their respective gates via contactholes. Each row conductor in the active plate may function as an addressconductor for supplying address signals to the gates of the TFTs in thecorresponding row. The row conductors may serve independently oradditionally to back up row conductors formed from the doped amorphoussilicon gate layer.

According to another aspect of the present invention, there is providedan electronic device comprising a bottom-gate TFT which comprises a gateof doped amorphous silicon on a substrate, a gate insulating layer oversaid gate and a polysilicon active layer over said gate insulatinglayer, said polysilicon active layer comprising an annealed amorphoussilicon layer.

Examples of the invention will now be described in detail with referenceto the accompanying drawings, in which:

FIG. 1 is a schematic plan view of part of an embodiment of an activeplate for an active matrix device manufactured by a method in accordancewith the present invention;

FIGS. 2A–2D show cross-sections on the line II—II of FIG. 1, at variousstages of fabrication, of a first embodiment of a device manufactured bya method in accordance with the present invention;

FIG. 3 shows a cross-section on the line III—III of FIG. 1 of the firstembodiment of a device manufactured by a method in accordance with thepresent invention;

FIG. 4 shows a highly enlarged perspective Scanning Electron Microscopy(SEM) image of part the first embodiment of a device manufactured by amethod in accordance with the present invention;

FIG. 5 shows a cross-section on the line III—III of FIG. 1 of a secondembodiment of a device manufactured by a method in accordance with thepresent invention;

FIG. 6 shows a highly enlarged perspective SEM image of part the secondembodiment of a device manufactured by a method in accordance with thepresent invention; and,

FIG. 7 is a simplified schematic circuit diagram of an active matrixliquid crystal display device manufactured by a method in accordancewith the present invention.

It should be noted that these figures are merely schematic and not drawnto scale. Relative dimensions and proportions of parts of these figureshave been shown exaggerated or reduced in size, for the sake of clarityand convenience in the drawings. The same reference numbers are usedthroughout the drawings to denote the same or similar parts.

The active plate 10 shown in part in FIG. 1 comprises an array of TFTs12 arranged in rows and columns, each TFT located at the intersection ofcrossing sets of row and column conductors 14 and 16. Only four TFTs 12are shown for simplicity but the active plate 10 may comprise severalhundreds of rows and columns. The active plate may form part of anactive matrix device such as an active matrix display device, forexample, having a corresponding array of display pixels, each displaypixel associated with a TFT of the active plate 10. By way of example,the active plate 10 shown in FIG. 1 forms part of an AMLCD having anarray of LC cells and in which a layer of LC material is sandwichedbetween the active plate 10 and a passive plate (not shown) carrying acommon electrode. Each cell has an associated pixel electrode 18 carriedon the active plate 10 and connected to a respective TFT 12. Thus, thevoltage applied across each LC cell, i.e. between each pixel electrode18 and the common electrode, can be controlled by its associated TFT 12.The general operation of this circuitry and the manner in which thedisplay pixels are driven follows conventional practice, as is describedfor example in U.S. Pat. No. 5,130,829 to which reference is invited forfurther information in these respects.

The TFTs 12 are FETs and each TFT has a source region 22 connected tothe associated column conductor 16, a drain region 24 connected to theassociated pixel electrode 18, a gate 26 connected to the associated rowconductor 14, and a polysilicon active layer 28 providing a channelwhich extends between the source and drain regions and which overliesthe gate 26.

FIG. 1 is drawn extremely diagrammatically in such a way as toillustrate two alternative embodiments of the present invention.

FIGS. 2A to 2D show cross-sections on the line II—II of FIG. 1, atvarious stages of fabrication, of a first embodiment of a devicemanufactured by a method in accordance with the present invention. FIG.3 shows a cross-section on the line III—III of the same device. Thecircuitry is formed using conventional thin film processing techniquesinvolving the deposition and photolithographic patterning of variousinsulating, conductive and semiconductive layers deposited on asubstrate 30, e.g. by a CVD process. The TFTs in the array are formedsimultaneously using common deposited layers.

Referring firstly to FIG. 3, a set of metal row conductors 14 is formedon a substrate 30 by depositing and patterning a metal layer of, say,aluminium. The substrate 30 here is of glass, although other insulatingmaterials such as polymer, paper or quartz can be used. Non-insulatingmaterials such as metal or silicon could also be used provided that atleast their upper surface is made insulating.

Referring now to FIG. 2A and FIG. 3, a doped amorphous silicon gatelayer 26′ is formed on the substrate, the gate layer having a smoothupper surface and defining a gate 26. The gate 26, for each TFT, isformed by depositing a layer of doped, n+ for example, amorphous silicondirectly over the substrate 30 and over the metal row conductor 14 andother row conductors 14 in the set to a thickness of between 5 nm and 10nm. This layer is then patterned to leave portions covering respectivemetal row conductors 14 and providing the gate 26 in the form of anintegral extension projecting outwardly from its associated rowconductor. The gate 26 is then taper etched, for example using a dryetch process, such that the gate slopes outwardly at its edges towardsthe substrate. The angle made between the tapered edges of the gate andthe substrate is between 10° and 30°. This facilitates good coverage ofthe overlying layers.

Following this, a gate insulating layer 32 of substantially uniformthickness is formed over the gate 26 as shown in FIG. 2B. This is doneby depositing a thin insulating layer over the entire surface of thesubstrate to a thickness in the range of between 1 nm and 40 nm, andpreferably between 1 nm and 5 nm. The smoothness of the doped amorphoussilicon gate upper surface allows a relatively thin gate insulatinglayer to be used. The gate insulating layer may comprise silicon oxide,silicon nitride, tantalum oxide, aluminium oxide, titanium oxide,hafnium oxide, zirconium oxide or any other suitable material with ahigh dielectric constant. Alternatively, the gate insulating layer maycomprise a pseudobinary alloy or a combination of more than one layer ofany of these materials.

Thereafter, an intrinsic (undoped) amorphous silicon active layer 28′ isformed over the gate insulating layer 32 and overlying at least part ofthe gate 26 by depositing the layer to a thickness of between 10 nm and100 nm, preferably around 40 nm, over the substrate 30 as shown in FIG.2C. Source and drain regions 22 and 24 for each TFT are then formed bydoping respective regions of the amorphous silicon layer 28′ by using amask layer for example. The amorphous silicon active layer 28′ is thenannealed to form a polysilicon active layer 28. Such annealing ofamorphous silicon to form polysilicon is well known and conventionalmethods in this respect can be used. Typically, energy beam 100irradiates the surface of the amorphous silicon layer 28′ so as to heatthe layer throughout its entire thickness. The energy beam 100 comprisesa pulsed laser beam of an ultra-violet wavelength generated by anexcimer laser. A pulsed laser beam 100 of ultra-violet wavelength hasthe known advantage of permitting control of its absorption depth in thesilicon layer 28′ and also control of the melt depth of this layer whenheated by the absorption of this pulsed laser energy. Useful laserwavelengths are 248 nm from a KrF laser, or a wavelength of 308 nm froma XeCl laser, or a wavelength of 351 nm from an XeF laser.

The doped amorphous silicon material of the gate 26 has a melting pointsimilar to that of the amorphous silicon layer 28′. Therefore, the meltdepth is chosen so that substantially the entire thickness of theamorphous silicon layer 28′ is melted without melting the gate 26, andthus the risk of delamination. On cooling, the amorphous silicon layer28′ becomes polycrystalline, as denoted at 28 in FIG. 2D with its uppersurface being roughened as typically is the case when amorphous siliconfilms are crystallised using a laser in this fashion. The polysiliconactive layer 28 is then patterned to leave respective portions extendingover the gates 26 at the locations of the TFTs constituting the activelayer islands of the TFTs, as shown in FIG. 2D and FIG. 3, each havingsource and drain regions 22 and 24 at opposite sides of the gate.

FIG. 4 shows a highly magnified perspective S.E.M image in part of thegate layer 26′ on the substrate 30 and the patterned polysilicon layer28 deposited and annealed using the method described above. It will beappreciated that S.E.M. images show only the surface topography. Thedark stripe 42 is a side-on view of the patterned active island 28 andgives an indication of the relative thickness′ of the layers. It can beseen that the gate layer 26′ remains smooth even after being subjectedto the conditions of the laser annealing process. The rough (top)surface of the polysilicon layer 28 can also be seen.

The annealing of the amorphous silicon layer 28′ causes at least anupper surface region of the gate layer 26′ to become microcrystalline bysolid phase crystallisation through consequential heating of the gatelayer. This, however, can be beneficial in improving the conductivity ofthe gate 26.

The smooth interface between the gate 26 and the gate insulating layer32 ensured by the use of amorphous silicon for the gate layer enablesthinner gate insulating layers of, say, a few nanometers in thickness,to be used, thus reducing the threshold voltage of the TFT.

A comparatively thick insulating layer 34 is then deposited over theentire substrate. This serves, inter alia, to separate the rowconductors 14 from the column conductors 16 at their crossover points inthe completed structure. Contact holes 36 are then formed in theinsulating layer 34 down to the source and drain regions 22 and 24 ofthe polysilicon active islands 28 for each TFT 12. Following this, ametal film, for example aluminium, is deposited over the substrate andpatterned to form both the set of metal column conductors 16 and the setof pixel electrodes 18. In the case of a reflective type AMLCD, thecolumn conductors 16 and pixel electrodes 18 are formed of a reflectivematerial such as aluminium., In the case of a transmissive type AMLCD, atransparent conducting material, such as ITO, is used. Each columnconductor 16 contacts with the source regions 22 of the TFTs in the samecolumn via the respective contact holes 36. Each pixel electrode 18contacts with the drain region 24 of its respective TFT via itsrespective contact hole 36. This completes the fabrication of the TFTsof the active plate 10 for an active matrix device.

FIG. 5 shows a cross-section on the line III—III of FIG. 1 of a secondembodiment of a device manufactured by a method in accordance with thepresent invention. The deposition and patterning of the gate layer 26′,the gate insulating layer 32 and the amorphous silicon layer 28′ iscarried out in the same way as that for the first embodiment asdescribed above. However, in this embodiment, the amorphous siliconlayer 28′ is patterned into islands before the annealing process.

Referring to FIG. 5, the amorphous silicon layer 28′ is patterned toleave respective portions constituting the active islands of the TFTsextending over a gate 26 at each of the locations of the TFTs. Followingthis, an energy beam corresponding to 100 in the first embodiment isdirected towards the substrate. As in the first embodiment, the energybeam is preferably a laser beam. The gate material has a melting pointsimilar to that of each of the amorphous silicon islands 28′. Therefore,the melt depth preferably is chosen so that substantially the entirethickness of each amorphous silicon island 28′ is melted without meltingthe gate 26. As before, on cooling, the silicon island 28 becomespolycrystalline with the upper surface now roughened. However, theannealing process causes portions of the gate layer 26′ not covered bythe amorphous silicon active layer (islands) to become polycrystalline.Therefore, the top surfaces of the polysilicon islands 28 and theexposed areas of the gate layer are roughened by the laser annealing.The surface of the metal row conductors 14 may also deform due to theheating from the laser. As shown in FIG. 5, this has an insignificanteffect on the functioning of these row conductors. FIG. 6 shows a highlymagnified perspective S.E.M. image in part of the device in which theamorphous silicon layer 28′ is patterned before the annealing process.As in FIG. 4 part of the gate layer 26′ and the overlying polysiliconisland 28 can be seen. However, the now exposed part of the gate layer26′ is partially polycrystalline and the roughened surface can be seenat 62. The gate 26 underlying the polysilicon island 28 (not visible inFIG. 6) remains amorphous, or at least partially microcrystalline, witha smooth surface.

Referring again to FIG. 5, then following the annealing process acomparatively thick insulating layer 34 is deposited over the entiresubstrate. This serves to separate the row conductors 14 from the columnconductors 16 in the finished structure. As in the first embodiment,contact holes 36 are then formed in the insulating layer 34 down to thesource and drain regions of the polysilicon active islands 28 for eachTFT 12.

In addition to those formed in the first embodiment, a contact hole 37is formed down to the gate layer 26′ for each TFT which contacts witheach respective gate 26. A conductive film, for example of aluminium orITO, is then deposited and patterned to form the column conductors 16,the pixel electrodes 18 and a top-gate 56 for each TFT. The top-gate 56overlies at least part of the polysilicon active layer 28 and thebottom-gate 26, with the insulating layer 34 serving as a gateinsulating layer for this second gate.

The top-gate 56 can be formed from the same deposition layer as thecolumn conductors 16 so that there are no extra deposition steps whencompared to the first embodiment. The top-gate contacts with the bottomgate via the contact hole 37. This provides an active plate 10 having anarray of dual-gated TFTs arranged in rows and columns. By including thisextra gate in each TFT, the operational characteristics of the deviceare improved.

Although the gate layer 26′ overlies the metal row conductors 14 in thetwo embodiments described above this is not essential. Instead the gatelayer 26′ may comprise the gates 26 which simply extend over and contactwith the metal row conductors 14. Alternatively, the set of metal rowconductors may be formed on top of the active plate after completion ofthe TFTs and insulated from the column conductors 16 and pixelelectrodes 18, and contact with a plurality of gates 26 in theirrespective row via a further series of contact holes.

FIG. 7 is a simplified schematic circuit diagram of an active matrixliquid crystal display (AMLCD) device manufactured by a method inaccordance with the present invention. The device comprises an activeplate 10 manufactured according to the invention, and having an array ofbottom-gate TFTs 12 arranged in rows and columns. The active plate alsocarries row and column conductors, 14 and 16, and pixel electrodes 18,each connected to an associated TFT 12. A layer of liquid crystal (LC)material is sandwiched between the active plate 10 and a passive plate70 forming an array of display pixels corresponding to the array ofTFTs. The pixel electrodes 18 are carried on the surface of the activeplate adjacent the LC layer. The passive plate comprises an insulatingsubstrate and carries on its inner surface adjacent the LC layer atransparent electrically conducting layer, for example ITO, whichextends continuously over the display area, corresponding to the area ofthe array of LC cells 72, and serves as a common electrode for thedisplay pixels.

Each pixel is addressed by row and column address circuitry, 74 and 76respectively, via the row and column conductors 14′ and 16. The addresscircuitry may be located remote from the active plate 10, as shown inFIG. 7, or integrated on the substrate 30, and formed by TFTs similar tothose of the pixel array and fabricated at the same time.

Although the above embodiments are described in relation to AMLCDs, theinvention is equally applicable to other active matrix display devicessuch as electroluminescent displays, electrophoretic displays andelectro-chromic displays. The invention is applicable also to otherkinds of active matrix array devices such as sensor array devices inwhich matrix sensing elements comprises, for example, optical sensingelements, as in image sensing array devices, or pressure or capacitivesensing elements, as in touch or fingerprint sensing array devices, andin which the matrix array of sensing elements are similarly addressedvia TFTs and sets of row and column conductors.

From reading the present disclosure, other modifications will beapparent to persons skilled in the art. Such modifications may involveother features which are already known in the field of electronicdevices comprising bottom-gate TFTs and component parts thereof andwhich may be used instead of or in addition to features alreadydescribed herein.

1. A method of manufacturing an electronic device comprising abottom-gate TFT, the method comprising the steps of: forming a dopedamorphous silicon gate layer on a substrate the gate layer defining agate; forming a gate insulating layer over the gate; forming anamorphous silicon active layer over the gate insulating layer andoverlying at least part of the gate; and annealing the amorphous siliconactive layer to form a polysilicon active layer wherein the annealingcauses a portion of the gate layer not covered by the amorphous siliconactive layer to become polycrystalline.
 2. A method according to claim 1wherein the gate layer thickness is between 5 nm and 10 nm.
 3. A methodaccording to claim 1, wherein the ate is tapered such that the edge ofthe gate slope outwardly towards the substrate.
 4. A method according toclaim 3, wherein the angle made between at least one tapered edge of thegate and the substrate is between 10° and 30°.
 5. A method according toclaim 1, wherein the gate insulating layer thickness is between 1 nm and40 nm.
 6. A method according to claim 1, wherein the gate insulatinglayer thickness is between 1 nm and 5 nm.
 7. A method according to claim1, wherein the amorphous silicon active layer thickness is between 10 nmand 100 nm.
 8. A method according to claim 7, wherein the method furthercomprises the steps of; forming a top-gate overlying at least part ofthe polysilicon active layer.
 9. A method according to claim 8, whereinthe electronic device comprises an active plate for an active matrixdevice, the active plate comprising an array of TFTs arranged in rowsand columns.
 10. A method according to claim 9, wherein the methodfurther comprises the step of: forming a set of row conductors, each rowconductor contacting with a plurality of gates in the same row.
 11. Amethod according to claim 10, wherein the electronic device comprises anactive matrix display device.
 12. A method of manufacturing anelectronic device comprising a bottom-gate TFT, the method comprisingthe steps of: forming a doped amorphous silicon gate layer sat asubstrate, the gate layer defining a plurality of gates with taperededges, and an upper surface region. a first portion and a secondportion; forming a gate insulating layer over the first portion of eachgate; forming an amorphous silicon active layer over the first portionof the gate. insulating layer and overlying at least part of each gate;and annealing the amorphous silicon active layer to cause at least theupper surface region of the gate layer to become microcrystalline, andto cause the second portion not covered by the amorphous silicon activelayer to become polycrystalline.
 13. A method according to claim 12,wherein the tapered edges of gates taper at an angle of between 10° and30° with respect to the substrate.
 14. A method according to claim 13,wherein the gate insulating layer has a thickness of between 1 nm and 5nm, and the amorphous silicon active layer has a thickness is between 10nm and 100 nm.
 15. A method according to claim 14, wherein the methodfurther comprises the step of: forming a set of row conductors, each rowconductor contacting the pularity of gates in the same row.